SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 234

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Differences Between the ARM9E-S and the ARM9TDMI
B-4
ARM9E-S signal
nFIQ
nIRQ
RDATA[31:0]
WDATA[31:0]
a. CLK is a rising edge clock. It is inverted with respect to the GCLK signal used on the ARM9TDMI hard macrocell.
b. CLKEN is sampled on the rising edge of CLK. The nWAIT signal on the ARM9TDMI hard macrocell must be held
c. All the address class signals (IA[31:1], DA[31:0], DnRW, DMAS, InTRANS, DnTRANS, and ITBIT) change on the
d. The ARM9TDMI featured a combinational path from DABORT to DnMREQ. This path does not exist in ARM9E-S.
e. With ARM9TDMI, the breakpoint and watchpoint inputs had to be asserted in the phase 1 of the cycle following the cycle in
f. All JTAG signals are synchronous to CLK on the ARM9E-S. There is no asynchronous TCK as on the ARM9TDMI hard
g. The DBGRQI signal in ARM9TDMI features a combinational input to output path from EDBGRQ. This has been removed
h. EDBGRQ must be synchronized externally to the macrocell. It is not an asynchronous input as on the ARM9TDMI hard
i. nFIQ and nIRQ are synchronous inputs to the ARM9E-S, and are sampled on the rising edge of CLK. Asynchronous
j. The ARM9E-S supports only unidirectional data buses, RDATA[31:0], and WDATA[31:0]. When a bidirectional bus is
throughout the high phase of GCLK. This means that the address class outputs (IA[31:1], DA[31:0], DnRW, DMAS,
InTRANS, DnTRANS, and ITBIT) can still change in a cycle in which CLKEN is taken LOW. You must take this
possibility into account when designing a memory system.
rising edge of CLK. In a system with a low-frequency clock this means that the signals can change in the first phase of the
clock cycle. This is unlike the ARM9TDMI hard macrocell where they always change in the last phase of the cycle.
which the data was returned from the memory system. With ARM9E-S, external breakpoints and watchpoints must be
returned in the same cycle as the data.
macrocell. An external synchronizing circuit can be used to generate TCLKEN when an asynchronous TCK is required.
However, CLK must be running.
in ARM9E-S.
macrocell.
interrupts are not supported.
required, you must implement external bus combining logic.
Table B-1 ARM9E-S signals and ARM9TDMI hard macrocell equivalents (continued)
Function
Fast interrupt request.
Interrupt request.
Data input bus.
Data output bus. This bus is always driven.
Copyright © 2000 ARM Limited. All rights reserved.
ARM9TDMI hard
macrocell equivalent
nFIQ
nIRQ
DDIN[31:0]
DD[31:0]
ARM DDI 0165B
Note
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i
j
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