SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 154

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7.8
7.8.1
7-16
The debug communications channel
Debug comms channel registers
The ARM9E-S EmbeddedICE-RT logic contains a communications channel for
passing information between the target and the host debugger. This is implemented as
coprocessor 14.
The communications channel comprises:
•
•
•
These registers are located in fixed locations in the EmbeddedICE-RT logic register
map (as shown in EmbeddedICE-RT logic on page C-28) and are accessed from the
processor using
In addition to the comms channel registers, the processor can access a 1-bit debug status
register for use in the monitor mode debug configuration.
Coprocessor 14 contains 4 registers, allocated as shown in Table 7-1.
Seen from the debugger, the registers are accessed using the scan chain in the usual way.
Seen from the processor, these registers are accessed using coprocessor register transfer
instructions.
Register name
Comms channel control
Comms channel data read
Comms channel data write
Comms channel monitor mode debug status
a. You can clear bit 0 of the comms channel control register by writing to it from the debugger
a 32-bit wide comms data read register
a 32-bit wide comms data write register
a 6-bit wide comms control register for synchronized handshaking between the
processor and the asynchronous debugger.
(JTAG) side.
Copyright © 2000 ARM Limited. All rights reserved.
MCR
and
MRC
instructions to coprocessor 14.
Table 7-1 Coprocessor 14 register map
Register
number
C0
C1
C1
C2
For writes
Notes
Read only
For reads
Read/write
ARM DDI 0165B
a