SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 113

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.2.4
ARM DDI 0165B
Interrupt registers
Example approaches are:
•
•
•
Before use, the nFIQ and nIRQ inputs are registered internally to the ARM9E-S. To
improve interrupt latency, the registers are not conditioned by CLKEN, and run freely,
off the system clock, CLK. Internally, the ARM9E-S can use the registered nFIQ or
nIRQ status to prepare for interrupt entry, even if the rest of the core is being waited by
CLKEN. The registered interrupt signals can only update if CLK is running. Because
of this, the best interrupt latency can only be achieved if CLK is not stopped. This
requirement is counteracted by power saving features of a system (for instance,
stopping CLK while waiting for a slow memory device, or a power-down mode where
CLK is stopped). In systems like this, you can still achieve the best interrupt latency if
you replace the final disabled CLK cycle with one waited (CLKEN = 0) cycle.
Figure 5-2 shows a system where CLK is stopped by external clock-gating for a
number of cycles.
Figure 5-3 on page 5-6 shows a system which achieves most of the power saving
benefits of the system shown in Figure 5-2, while at the same time achieving best
interrupt latency.
Analyze the system and ensure enough instructions separate the instruction that
removes the interrupt and the instruction that re-enables interrupts on the
ARM9E-S.
Have a software polling mechanism that reads back a status bit from the system
interrupt controller until it indicates that the interrupt has been removed before
re-enabling interrupts.
Have a hardware system that stalls the ARM9E-S until the interrupt has been
removed.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 5-2 Stopping CLK for power saving
Interrupts
5-5