SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 91

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.8
4.8.1
4.8.2
ARM DDI 0165B
Data interface addressing signals
DA[31:0]
DnRW
The address class signals are:
•
•
•
•
•
•
DA[31:0] is the 32-bit address bus that specifies the address for the transfer. All
addresses are byte addresses, so a burst of word accesses results in the address bus
incrementing by 4 for each cycle.
The address bus provides 4GB of linear addressing space. When a word access is
signaled the memory system must ignore the bottom two bits, DA[1:0], and when a
halfword access is signaled the memory system must ignore the bottom bit, DA[0].
DnRW specifies the direction of the transfer. DnRW indicates an ARM9E-S write
cycle when HIGH, and an ARM9E-S read cycle when LOW. A burst of S cycles is
always either a read burst, or a write burst, because the direction cannot be changed in
the middle of a burst.
You must not initiate writes to memory purely on the basis of DnRW. You must use the
status of the data interface request signals to condition writes to memory. See Data
interface cycle types on page 4-24 for more details.
DA[31:0]
DnRW
DMAS[1:0] on page 4-16
DnTRANS on page 4-16
DLOCK on page 4-17
DnM[4:0] on page 4-17.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Memory Interface
4-15