SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 63

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.9.2
2.9.3
ARM DDI 0165B
Entering an exception
Leaving an exception
When handling an exception the ARM9E-S:
1.
2.
3.
4.
The ARM9E-S can also set the interrupt disable flags to prevent otherwise
unmanageable nesting of exceptions.
Exceptions are always entered, handled, and exited in ARM state. When the processor
is in Thumb state and an exception occurs, the switch to ARM state takes place
automatically when the exception vector address is loaded into the PC.
When an exception has completed, the exception handler must move the LR, minus an
offset to the PC. The offset varies according to the type of exception, as shown in
Table 2-3 on page 2-20.
If the S bit is set and rd = r15, the core copies the SPSR back to the CPSR and clears
the interrupt disable flags that were set on entry.
The action of restoring the CPSR from the SPSR automatically resets the T bit to the
value it held immediately prior to the exception. The I and F bits are automatically
restored to the value they held immediately prior to the exception.
Preserves the address of the next instruction in the appropriate LR. When the
exception entry is from:
•
•
The exception handler does not need to determine the state when entering an
exception. For example, in the case of a SWI,
returns to the next instruction regardless of whether the SWI was executed in
ARM or Thumb state.
Copies the CPSR into the appropriate SPSR.
Forces the CPSR mode bits to a value which depends on the exception.
Forces the PC to fetch the next instruction from the relevant exception vector.
Note
Note
Copyright © 2000 ARM Limited. All rights reserved.
LR (current PC + 4 or PC + 8 depending on the exception).
by a value (current PC + 4 or PC + 8 depending on the exception) that
causes the program to resume from the correct place on return.
ARM state, the ARM9E-S copies the address of the next instruction into the
Thumb state, the ARM9E-S writes the value of the PC into the LR, offset
MOVS PC, r14_svc
Programmer’s Model
always
2-21