SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 203

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SAM9XE512

Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9XE512

Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
8.25
ARM DDI 0165B
Cycle
ready
not ready
a. IREQ = InMREQ, ISEQ.
b. DREQ = DnMREQ, DSEQ.
c. P = PASS.
d. LC = LATECANCEL.
Coprocessor register transfer (from ARM)
1
1
.
n
n+1
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
The move to coprocessor (
coprocessor register.
Data is transferred over the data bus interface, in a similar fashion to a store register
operation.
An interrupt can cause the ARM9E-S to abandon a busy-waiting coprocessor
instruction (see Busy-waiting and interrupts on page 6-17).
Coprocessor operations are only available in ARM state.
The
MCR
IREQ
S cycle
I cycle
I cycle
I cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction cycle timings are shown in Table 8-32.
a
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
-
-
(pc+3i)
-
MCR
DA
-
-
-
-
-
) operation transfers a specified ARM register to a
DREQ
C cycle
I cycle
C cycle
I cycle
I cycle
b
Table 8-32 MCR instruction cycle timing
WDATA
Rd
-
-
Rd
-
P
1
1
1
1
1
c
LC
0
0
0
0
0
d
Instruction Cycle Times
CHSD
LAST
WAIT
CHSE
-
WAIT
WAIT
LAST
-
8-43

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