SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 66

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.9.8
2-24
Software interrupt instruction
The SWI handler reads the opcode to extract the SWI function number.
IRQs are disabled when a software interrupt occurs.
The ARM9E-S implements the base restored Data Abort model, which differs from the
base updated Data Abort model implemented by the ARM7TDMI-S.
The difference in the Data Abort model affects only a very small section of operating
system code, in the Data Abort handler. It does not affect user code.
With the base restored Data Abort model, when a Data Abort exception occurs during
the execution of a memory access instruction, the base register is always restored by the
processor hardware to the value it contained before the instruction was executed. This
removes the need for the Data Abort handler to unwind any base register update, which
might have been specified by the aborted instruction. This greatly simplifies the
software Data Abort handler.
The abort mechanism allows you to implement a demand-paged virtual memory
system. In such a system, the processor is allowed to generate arbitrary addresses. When
the data at an address is unavailable, the Memory Management Unit (MMU) signals an
abort. The abort handler must then work out the cause of the abort, make the requested
data available, and retry the aborted instruction. The application program needs no
knowledge of the amount of memory available to it, and its state is not affected by the
abort.
After dealing with the cause of the abort, the handler must execute the following return
instruction irrespective of the processor operating state at the point of entry:
SUBS PC,R14_abt,#8
This action restores both the PC and the CPSR, and retries the aborted instruction.
You can use the Software Interrupt Instruction (
to request a particular supervisor function. A SWI handler returns by executing the
following instruction, irrespective of the processor operating state:
MOVS PC, R14_svc
This action restores the PC and CPSR, and returns to the instruction following the
Copyright © 2000 ARM Limited. All rights reserved.
SWI
) to enter Supervisor mode, usually
ARM DDI 0165B
SWI
.