SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 174

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.8
8-14
MRS
An
pending state changes to the PSR to be made. The second cycle passes the PSR register
through the ALU so that it can be written to the destination register.
The
Table 8-9 shows the
Cycle
1
2
MRS
MRS
Note
Copyright © 2000 ARM Limited. All rights reserved.
operation always takes two cycles to execute. The first cycle allows any
instruction can only be executed when in ARM state.
IA
pc+3i
pc+3i
MRS
InMREQ,
ISEQ
I cycle
S cycle
cycle timing.
INSTR
(pc+2i)
-
(pc+3i)
DA
-
-
Table 8-9 MRS cycle timing
DnMREQ,
DSEQ
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-