SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 196

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.20
8-36
Cycle
1
2
3
Software interrupt, undefined instruction, and exception entry
IA
Xn
Xn+4
Xn+8
InMREQ,
ISEQ
N cycle
S cycle
S cycle
Exceptions, software interrupts (SWIs), and undefined instructions force the PC to a
specific value and refill the instruction pipeline from this address:
1.
2.
3.
The exception entry cycle timings are show in Table 8-27, where:
pc
Xn
The value on the INSTR bus can be unpredictable in the case of Prefetch Abort or Data
Abort entry.
During the first cycle, the ARM9E-S constructs the forced address, and a mode
change might take place.
During the second cycle, the ARM9E-S performs a fetch from the exception
address. The return address to be stored in r14 is calculated. The state of the CPSR
is saved in the relevant SPSR.
During the third cycle, the ARM9E-S performs a fetch from the exception address
+ 4, refilling the instruction pipeline.
Note
Copyright © 2000 ARM Limited. All rights reserved.
InTRANS
1
1
1
Is one of:
•
•
•
•
Is the appropriate exception address.
the address of the
the address of the instruction following the last one to be executed
before entering the exception for interrupts
the address of the aborted instruction for Prefetch Aborts
the address of the instruction following the one that attempted the
aborted data transfer for Data Aborts.
ITBIT
0
0
0
SWI
INSTR
(Xn)
(Xn+4)
(Xn+8)
instruction for SWIs
Table 8-27 Exception entry cycle timing
DA
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-