SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 224

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Signal Descriptions
A.3
A-4
Data memory interface signals
The data memory interface signals are shown in Table A-3.
Name
DA[31:0]
Data address
DABORT
Data abort
RDATA [31:0]
Read data
WDATA [31: 0]
Write data
DBGDEWPT
Data watchpoint
DLOCK
Data lock
DMAS[1:0]
Data memory
access size
DMORE
Data more
DnMREQ
Not data memory
request
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Input
Input
Output
Input
Output
Output
Output
Output
Description
The processor data address bus.
This is an input that allows the memory system
to tell the processor that the requested data
memory access is not allowed.
This bus is used to transfer data between the
memory system and the processor during read
cycles (when DnRW is LOW).
This bus is used to transfer data between the
memory system and the processor during write
cycles (when DnRW is HIGH).
This is an input that allows external hardware to
halt the execution of the processor for debug
purposes. If HIGH at the end of a data memory
request cycle, it causes the ARM9E-S to enter
debug state.
If HIGH, then any data memory access in the
following cycle is locked, and the memory
controller must wait until DLOCK goes LOW
before allowing another device to access the
memory.
These encode the size of a data memory access
in the following cycle. A word access is
encoded as 10 (binary), a halfword access as 0l,
and a byte access as 00. The encoding 11 is
reserved.
If HIGH at the end of the cycle, then the data
memory access in the following cycle is
directly followed by a sequential data memory
access.
If LOW at the end the cycle, then the processor
requires a data memory access in the following
cycle.
Table A-3 Data memory interface signals
ARM DDI 0165B