SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 183

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
Cycle
Normal
dest=pc
1
1
2
3
4
5
IA
pc+3i
pc+3i
pc+3i
pc’
pc’+i
pc’+2i
The following example incurs a second-cycle interlock:
LDR
STMIA
A second-cycle interlock can be incurred on the first word of data stored by an
instruction or during the first cycle of a register controlled shift. The following example
does not incur an interlock:
LDR
STMIA
Table 8-18 shows the cycle timing for basic load register operations, where:
s
t
Destination equals PC is not possible in Thumb state.
InMREQ,
ISEQ
S cycle
I cycle
I cycle
N cycle
S cycle
S cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
r0, [r1]
r2, {r0-r1}
r3, [r1]
r0, {r2-r3}
Represents the current mode-dependent value.
Is either 0, when the T bit is specified in the instruction (for example
LDRT
) or s at all other times.
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
-
(pc+3i)
(pc’)
(pc’+i)
(pc’+2i)
DA
da
da
-
-
-
-
Table 8-18 Load register operation cycle timing
DnMREQ,
DSEQ
N cycle
N cycle
I cycle
I cycle
I cycle
I cycle
DnTRANS
t
t
s
s
s
s
Instruction Cycle Times
RDATA
(da)
(da)
-
-
-
-
STM
8-23