SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 103

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.10.2
ARM DDI 0165B
Data interface, sequential cycles
If you are designing a memory controller for the ARM9E-S, and your memory system
is unable to cope with this case, use the CLKEN signal to extend the bus cycle to allow
sufficient cycles for the memory system (see Use of CLKEN to control bus cycles on
page 4-31).
Sequential cycles perform burst transfers on the bus. You can use this information to
optimize the design of a memory controller interfacing to a burst memory device, such
as a DRAM.
During a sequential cycle, the ARM9E-S requests a memory location that is part of a
sequential burst. If this is the first cycle in the burst, the address can be the same as the
previous internal cycle. Otherwise the address is incremented from the previous cycle.
For a burst of word accesses, the address is incremented by 4 bytes.
Bursts of halfword or byte accesses are not possible on the ARM9E-S data interface.
A burst always starts with an N cycle and continues with S cycles. A burst comprises
transfers of the same type. The DA[31:0] signal increments during the burst. The other
address class signals are unaffected by a burst.
CLK
Address class
signals
DnRW
DnMREQ,
DSEQ,
DMORE
WDATA[31:0]
(Write)
RDATA[31:0]
(Read)
Copyright © 2000 ARM Limited. All rights reserved.
Write address
N cycle
Write cycle
Figure 4-10 Back to back memory cycles
Read address
Write data
N cycle
Read cycle
Read data
Memory Interface
4-27