SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 20

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Introduction
1.1
1.1.1
1-2
About the ARM9E-S
The instruction pipeline
The ARM9E-S is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low power
consumption and gate count.
The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The reduced instruction set and related decode mechanism are much simpler
than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
•
•
•
The ARM9E-S supports the ARMv5TE architecture and features an enhanced
multiplier design for improved DSP performance.
The ARM9E-S supports the ARM debug architecture and features support for real-time
debug, which allows critical exception handlers to execute while debugging the system.
The ARM9E-S uses a pipeline to increase the speed of the flow of instructions to the
processor. This allows several operations to take place simultaneously, and the
processing and memory systems to operate continuously.
A five-stage pipeline is used, consisting of Fetch, Decode, Execute, Memory, and
Writeback stages. This is shown in Figure 1-1 on page 1-3.
a high instruction throughput
an excellent real-time interrupt response
a small, cost-effective, processor macrocell.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B