SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 67

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.9.9
2.9.10
ARM DDI 0165B
Undefined instruction
Breakpoint instruction (BKPT)
When an instruction is encountered that neither the ARM9E-S, nor any coprocessor in
the system can handle, the ARM9E-S takes the undefined instruction trap. Software can
use this mechanism to extend the ARM instruction set by emulating undefined
coprocessor instructions.
After emulating the failed instruction, the trap handler executes the following
instruction, irrespective of the processor operating state:
MOVS PC,R14_und
This action restores the CPSR and returns to the next instruction after the undefined
instruction.
IRQs are disabled when an undefined instruction trap occurs. For more information
about undefined instructions, refer to the ARM Architecture Reference Manual.
A breakpoint (
Abort.
A breakpoint instruction does not cause the ARM9E-S to take the Prefetch Abort
exception until the instruction reaches the Execute stage of the pipeline. If the
instruction is not executed, for example because a branch occurs while it is in the
pipeline, the breakpoint does not take place.
After dealing with the breakpoint, the handler executes the following instruction
irrespective of the processor operating state:
SUBS PC,R14_abt,#4
This action restores both the PC and the CPSR, and retries the breakpointed instruction.
If the EmbeddedICE-RT logic is configured into stopping mode, a breakpoint
instruction causes the ARM9E-S to enter debug state. See Debug control register on
page C-34.
Note
Copyright © 2000 ARM Limited. All rights reserved.
BKPT
) instruction operates as though the instruction caused a Prefetch
Programmer’s Model
2-25