SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 168

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.3
8-8
Branch and ARM branch with link
Any ARM or Thumb branch, and an ARM branch with link operation takes three
cycles:
1.
2.
3.
Cycle
1
2
3
During the first cycle, a branch instruction calculates the branch destination while
performing a prefetch from the current PC. This prefetch is performed in all case,
because by the time the decision to take the branch has been reached, it is already
too late to prevent the prefetch. If the previous instruction requested a data
memory access, the data is transferred in this cycle.
During the second cycle, the ARM9E-S performs a fetch from the branch
destination. If the link bit is set, the return address to be stored in r14 is calculated.
During the third cycle, the ARM9E-S performs a fetch from the destination + i,
refilling the instruction pipeline.
Copyright © 2000 ARM Limited. All rights reserved.
IA
pc’
pc’ + i
pc’ + 2i
InMREQ,
ISEQ
N cycle
S cycle
S cycle
Table 8-4 Branch and ARM branch with link cycle timings
INSTR
(pc + 2i)
(pc’)
(pc’ + i)
(pc’ + 2i)
DA
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-