SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 249

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.4.5
C.4.6
C.4.7
ARM DDI 0165B
IDCODE (1110)
BYPASS (1111)
RESTART (0100)
The IDCODE instruction connects the device identification code register (or
ID register) between DBGTDI and DBGTDO. The ID register is a 32-bit register that
allows the manufacturer, part number, and version of a component to be read through
the TAP. See ARM9E-S device identification (ID) code register on page C-10 for details
of the ID register format.
When the IDCODE instruction is loaded into the instruction register, all the scan cells
are placed in their normal (System) mode of operation:
•
•
•
The BYPASS instruction connects a 1-bit shift register (the bypass register) between
DBGTDI and DBGTDO.
When the BYPASS instruction is loaded into the instruction register, all the scan cells
assume their normal (System) mode of operation. The BYPASS instruction has no
effect on the system pins:
•
•
•
All unused instruction codes default to the BYPASS instruction.
The RESTART instruction is used to restart the processor on exit from debug state. The
RESTART instruction connects the bypass register between DBGTDI and DBGTDO,
and the TAP controller behaves as if the BYPASS instruction has been loaded.
The processor exits debug state when the RUN-TEST/IDLE state is entered.
In the CAPTURE-DR state, the device identification code is captured by the ID
register.
In the SHIFT-DR state, the previously captured device identification code is
shifted out of the ID register via the DBGTDO pin, while data is shifted into the
ID register through the DBGTDI pin.
In the UPDATE-DR state, the ID register is unaffected.
In the CAPTURE-DR state, a logic 0 is captured in the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register through
DBGTDI, and shifted out through DBGTDO after a delay of one CLK cycle.
The first bit to shift out is a zero.
The bypass register is not affected in the UPDATE-DR state.
Copyright © 2000 ARM Limited. All rights reserved.
Debug in depth
C-9