SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 238

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Differences Between the ARM9E-S and the ARM9TDMI
B.4.4
B.4.5
B-8
Address class signal timing
Data Aborts
The address class outputs (IA[31:1], DA[31:0], DnRW, DMAS, InTRANS,
DnTRANS, and ITBIT) on the ARM9E-S all change in response to the rising edge of
CLK. This means that they can change in the first phase of the clock in some systems.
When exact compatibility is required, add latches to the outside of the ARM9E-S to
make sure that they can change only in the second phase of the clock.
Because the CLKEN signal is sampled only on the rising edge of the clock, the address
class outputs still change in a cycle in which CLKEN is LOW. (This is similar to the
behavior of I/DnMREQ and I/DSEQ in an ARM9TDMI hard macrocell system, when
a wait state is inserted using nWAIT.) Make sure that the memory system design takes
this into account.
Also make sure that the correct address is used for the memory cycle, even though
IA/DA[31:0] might have moved on to the address for the next memory cycle.
For further details, refer to Chapter 4 Memory Interface.
The ARM9TDMI featured a combinational path from DABORT to DnMREQ, DSEQ,
and DMORE. This path does not exist in ARM9E-S. A consequence of this change is
that, in the case of two back-to-back memory accesses (for example a load followed by
a store), the second access is not canceled by the ARM processor if the first is aborted.
In these situations, the system must ignore the second memory request. For more
details, see DABORT on page 4-18.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B