SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 64

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.9.4
2.9.5
2.9.6
2-22
Reset
Fast interrupt request
Interrupt request
When the nRESET signal is driven LOW a reset occurs, and the ARM9E-S abandons
the executing instruction.
When nRESET is driven HIGH again the ARM9E-S:
1.
2.
3.
After reset, all register values except the PC and CPSR are indeterminate.
Refer to Chapter 3 Device Reset for more details of the ARM9E-S reset behavior.
The Fast Interrupt Request (FIQ) exception supports fast interrupts. In ARM state, FIQ
mode has eight private registers to reduce, or even remove the requirement for register
saving (minimizing the overhead of context switching).
An FIQ is externally generated by taking the nFIQ signal input LOW. The nFIQ input
is registered internally to the ARM9E-S. It is the output of this register that is used by
the ARM9E-S control logic.
Irrespective of whether exception entry is from ARM state or from Thumb state, an FIQ
handler returns from the interrupt by executing:
SUBS PC,R14_fiq,#4
You can disable FIQ exceptions within a privileged mode by setting the CPSR F flag.
When the F flag is clear, the ARM9E-S checks for a LOW level on the output of the
nFIQ register at the end of each instruction.
FIQs and IRQs are disabled when an FIQ occurs. Nested interrupts are allowed but it is
up to the programmer to save any corruptible registers and to re-enable FIQs and
interrupts.
The Interrupt Request (IRQ) exception is a normal interrupt caused by a LOW level on
the nIRQ input. IRQ has a lower priority than FIQ, and is masked on entry to an FIQ
sequence. You can disable IRQ at any time, by setting the I bit in the CPSR from a
privileged mode.
Forces CPSR[4:0] to b10011 (Supervisor mode), sets the I and F bits in the CPSR,
and clears the CPSR T bit. Other bits in the CPSR are indeterminate.
Forces the PC to fetch the next instruction from the reset vector address.
Reverts to ARM state, and resumes execution.
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B