SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 172

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.7
8-12
Data operations
A normal data operation executes in a single execute cycle except where the shift is
determined by the contents of a register. A normal data operation requires up to two
operands, that are read from the register file onto the A and B buses.
The ALU combines the A bus operand with the (shifted) B bus operand according to
the operation specified in the instruction. The ARM9E-S pipelines this result and writes
it into the destination register, when required. Compare and test operations do not write
a result as they only affect the status flags.
An instruction prefetch occurs at the same time as the data operation, and the PC is
incremented.
When a register specified shift is used, an additional execute cycle is needed to read the
shifting register operand. The instruction prefetch occurs during this first cycle.
The PC can be one or more of the register operands. When the PC is the destination, the
external bus activity is affected. When the ARM9E-S writes the result to the PC, the
contents of the instruction pipeline are invalidated, and the ARM9E-S takes the address
for the next instruction prefetch from the ALU rather than the incremented address. The
ARM9E-S refills the instruction pipeline before any further instruction execution takes
place. Exceptions are locked out while the pipeline is refilling.
Shifted register with destination equals PC is not possible in Thumb state.
The data operation cycle timings are shown in Table 8-8.
Cycle
Normal
dest=pc
Note
Copyright © 2000 ARM Limited. All rights reserved.
1
1
2
3
pc+3i
IA
pc’
pc’+ i
pc’+2i
InMREQ,
ISEQ
S cycle
N cycle
S cycle
S cycle
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
(pc’)
(pc’+i)
(pc’+ 2i)
Table 8-8 Data operation cycle timing
DA
-
-
-
-
DnMREQ,
DSEQ
I cycle
I cycle
I cycle
I cycle
ARM DDI 0165B
RDATA/
WDATA
-
-
-
-