SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 163

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1
ARM DDI 0165B
Instruction
CLZ
Data Op
Data Op
Data Op
Data Op
LDR
LDR
LDR
LDR
Instruction cycle count summary
Cycles
1
1
2
3
4
1
2
3
5
Table 8-1 shows the key to the other tables in this chapter.
Table 8-2 summarizes the ARM9E-S instruction cycle counts and bus activity when
executing the ARM instruction set.
Symbol
b
n
C
I
N
S
Copyright © 2000 ARM Limited. All rights reserved.
Instruction
bus
1S
1S
1S+1I
2S+1N
2S+1N+1I
1S
1S+1I
1S+2I
2S+2I+1N
Meaning
The number of busy-wait states during coprocessor accesses.
The number of words transferred in an LDM/STM/LDC/STC.
Coprocessor register transfer cycle (C-cycle).
Internal cycle (I-cycle).
Nonsequential cycle (N-cycle).
Sequential cycle (S-cycle).
Data
bus
1I
1I
2I
3I
4I
1N
1N+1I
1N+2I
1N+4I
Loaded byte, halfword, or unaligned word used
PC is destination register.
Comment
All cases.
Normal case, PC not destination.
With register controlled shift, PC not
destination.
PC destination register.
With register controlled shift, PC destination
register.
Normal case, not loading PC.
Not loading PC and following instruction uses
loaded word (1 cycle load-use interlock).
by following instruction (2-cycle load-use
interlock).
Table 8-2 ARM instruction cycle counts
Table 8-1 Key to tables
Instruction Cycle Times
8-3