SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 22

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Introduction
1.1.2
1.1.3
1-4
CLK
IA[31:1], InMREQ,
ISEQ
INSTR[31:0]
DA[31:0], DnMREQ,
DSEQ, DMORE
WDATA[31:0]
RDATA[31:0]
Memory access
Forwarding, interlocking and data dependencies
Typical pipeline operation is shown in Figure 1-2.
The ARM9E-S has a Harvard architecture. This features separate address and data
buses for both the 32-bit instruction interface and the 32-bit data interface. This
achieves a significant decrease in Cycles Per Instruction (CPI) by allowing instruction
and data accesses to run concurrently.
Only load, store, coprocessor load, coprocessor store, and swap instructions can access
data from memory. Data can be 8-bit bytes, 16-bit halfwords or 32-bit words. Words
must be aligned to 4-byte boundaries. Halfwords must be aligned to 2-byte boundaries.
Due to the nature of the five-stage pipeline, it is possible for a value to be required for
use before it has been placed in the register bank by the actions of an earlier instruction.
The ARM9E-S control logic automatically detects these cases and stalls the core or
forwards data as applicable to overcome these hazards. No intervention is required by
software in these cases, although you can improve software performance by re-ordering
instructions in certain situations.
Copyright © 2000 ARM Limited. All rights reserved.
memory access
Instruction
F
Register
decode
D
Register
read
Shift
multiply cycle
First
E
ALU
Figure 1-2 The instruction pipeline
memory access
multiply cycle
Second
Data
M
Register
write
W
ARM DDI 0165B