SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 248

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C.4.3
C.4.4
C-8
SCAN_N (0010)
INTEST (1100)
The SCAN_N instruction connects the scan path select register between DBGTDI and
DBGTDO:
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The scan path select register is 4 bits long in this implementation, although no finite
length is specified.
The INTEST instruction places the selected scan chain in test mode:
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Single-step operation of the core is possible using the INTEST instruction.
In the CAPTURE-DR state, the fixed value
In the SHIFT-DR state, the ID number of the desired scan path is shifted into the
scan path select register.
In the UPDATE-DR state, the scan register of the selected scan chain is connected
between DBGTDI and DBGTDO, and remains connected until a subsequent
SCAN_N instruction is issued.
On reset, scan chain 0 is selected by default.
The INTEST instruction connects the selected scan chain between DBGTDI and
DBGTDO.
When the INTEST instruction is loaded into the instruction register, all the scan
cells are placed in their test mode of operation. For example, in test mode, input
cells select the output of the scan chain to be applied to the core.
In the CAPTURE-DR state, the value of the data applied from the core logic to
the output scan cells, and the value of the data applied from the system logic to
the input scan cells is captured.
In the SHIFT-DR state, the previously-captured test data is shifted out of the scan
chain via the DBGTDO pin, while new test data is shifted in via the DBGTDI
pin.
Copyright © 2000 ARM Limited. All rights reserved.
1000
is loaded into the register.
ARM DDI 0165B