SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 232

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Differences Between the ARM9E-S and the ARM9TDMI
B.1
B-2
ARM9E-S signal
CFGBIGEND
CFGDISLTBIT
CFGHIVECS
CLK
CLKEN
DA[31:0]
DABORT
DBGCOMMRX
DBGCOMMTX
DBGDEWPT
Interface signals
Function
1 = big-endian configuration.
0 = little-endian configuration.
1 = disable specific ARMv5T behavior.
0 = enable (default).
1 = exception vectors start at 0xFFFF 0000.
0 = exception vectors start at 0x0000 0000.
Rising edge master clock. All inputs are sampled on the
rising edge of CLK.
All timing dependencies are from the rising edge of CLK.
System memory interface clock enable:
1 = advance the core on rising CLK.
0 = prevent the core advancing on rising CLK.
32-bit data address output bus, available in the cycle
preceding the memory cycle.
Data Abort.
EmbeddedICE communication channel receive buffer full
output.
EmbeddedICE communication channel transmit buffer
empty output.
External data watchpoint (tie LOW when not used).
The signal names have prefixes that identify groups of functionally-related signals:
CFG
CP
DBG
Other signals provide the interface for the system designer, which is primarily
memory-mapped. Table B-1 shows the ARM9E-S signals with their ARM9TDMI hard
macrocell equivalent signals.
Copyright © 2000 ARM Limited. All rights reserved.
Table B-1 ARM9E-S signals and ARM9TDMI hard macrocell equivalents
Shows configuration inputs (typically hard-wired for an embedded
application).
Shows coprocessor expansion interface signals.
Shows scan-based EmbeddedICE debug support input or output.
ARM9TDMI hard
macrocell equivalent
BIGEND
-
HIVECS
GCLK
nWAIT
DA[31:0]
DABORT
COMMRX
COMMTX
DEWPT
ARM DDI 0165B
Note
-
-
-
a
b
c
d
-
-
e