SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 151

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.5.4
7.5.5
7.5.6
ARM DDI 0165B
Watchpoints and exceptions
Debug request
Actions of the ARM9E-S in debug state
If there is an abort with the data access as well as a watchpoint, the watchpoint condition
is latched, the exception entry sequence is performed, and then the processor enters
debug state. If there is an interrupt pending, the ARM9E-S allows the exception entry
sequence to occur and then enters debug state.
A debug request can take place through the EmbeddedICE-RT logic or by asserting the
EDBGRQ signal. The request is registered and passed to the processor. Debug request
takes priority over any pending interrupt. Following registering, the core enters debug
state when the instruction at the Execute stage of the pipeline has completely finished
executing (once Memory and Write stages of the pipeline have completed). While
waiting for the instruction to finish executing, no more instructions are issued to the
Execute stage of the pipeline.
When a debug request occurs, the ARM9E-S enters debug state even if the
EmbeddedICE-RT is configured for monitor mode debug.
Once the ARM9E-S is in debug state, both memory interfaces indicate internal cycles.
This allows the rest of the memory system to ignore the ARM9E-S and function as
normal. Because the rest of the system continues operation, the ARM9E-S ignores
aborts and interrupts.
The CFGBIGEND signal must not be changed by the system while in debug state. If it
changes, not only is there a synchronization problem, but the view of the ARM9E-S
seen by the programmer changes without the knowledge of the debugger. The nRESET
signal must also be held stable during debug. If the system applies reset to the
ARM9E-S (nRESET is driven LOW), the state of the ARM9E-S changes without the
knowledge of the debugger.
Copyright © 2000 ARM Limited. All rights reserved.
Debug Interface and EmbeddedICE-RT
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