SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 148

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7.5.2
7-10
Breakpoints and exceptions
undefined instruction.
On an instruction boundary, if there is a breakpointed instruction and an interrupt
(nIRQ or nFIQ), the interrupt is taken and the breakpointed instruction is discarded.
When the interrupt has been serviced, the execution flow is returned to the original
program. This means that the instruction which was previously breakpointed is fetched
again, and if the breakpoint is still set, the processor enters debug state when it reaches
the execute stage of the pipeline.
When the processor has entered debug state, it is important that further interrupts do not
affect the instructions executed. For this reason, as soon as the processor enters debug
state, interrupts are disabled, although the state of the I and F bits in the Program Status
Register (PSR) are not affected.
A breakpointed instruction is allowed to enter the Execute stage of the pipeline, but any
state change as a result of the instruction is prevented. All instructions prior to the
breakpointed instruction complete as normal.
If a breakpointed instruction does not reach the Execute stage, for instance, if an earlier
instruction is a branch, then both the breakpointed instruction and breakpoint status are
discarded and the ARM does not enter debug state.
The Decode cycle of the debug entry sequence occurs during the execute cycle of the
breakpointed instruction. The latched Breakpoint signal forces the processor to start
the debug sequence.
In Figure 7-4 on page 7-9 instruction B is breakpointed. The debug entry sequence is
initiated when instruction B enters the Execute stage. The ARM completes the debug
entry sequence and asserts DBGACK two cycles later.
A breakpointed instruction can have a Prefetch Abort associated with it. If so, the
Prefetch Abort takes priority and the breakpoint is ignored. (If there is a Prefetch Abort,
instruction data might be invalid, the breakpoint might have been data-dependent, and
as the data might be incorrect, the breakpoint might have been triggered incorrectly.)
SWI
can have a breakpoint set on it. Therefore, the breakpoint takes priority over the
and undefined instructions are treated in the same way as any other instruction that
Note
Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
SWI
or