SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 84

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.6
4-8
Instruction interface cycle types
The ARM9E-S instruction interface is pipelined. The address class signals and the
memory request signals are broadcast in the bus cycle ahead of the bus cycle to which
they refer. This gives the maximum time for a memory cycle to decode the address, and
respond to the access request.
A single memory cycle is shown in Figure 4-1.
The ARM9E-S instruction interface can perform three different types of memory cycle.
These are indicated by the state of the InMREQ and ISEQ signals. Memory cycle
types are encoded on the InMREQ and ISEQ signals as shown in Table 4-6.
A memory controller for the ARM9E-S must commit to an instruction memory access
only on an N cycle or an S cycle.
InMREQ
0
0
1
1
Copyright © 2000 ARM Limited. All rights reserved.
CLK
InMREQ,
ISEQ
Address class
signals
INSTR[31:0]
ISEQ
0
1
0
1
Cycle type
N cycle
S cycle
I cycle
-
Cycle type
Address
Figure 4-1 Simple memory cycle
Bus cycle
Description
Nonsequential cycle
Sequential cycle
Internal cycle
Reserved
Instruction
Table 4-6 Cycle types
data
ARM DDI 0165B