SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 78

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Memory Interface
4.1
4-2
About the memory interface
The ARM9E-S has a Harvard bus architecture with separate instruction and data
interfaces. This allows concurrent instruction and data accesses, and greatly reduces the
Cycles Per Instruction (CPI) of the processor. For optimal performance, single-cycle
memory accesses for both interfaces are required, although the core can be wait-stated
for nonsequential accesses, or slower memory systems.
For both instruction and data interfaces, the ARM9E-S processor core uses pipelined
addressing. This means that the address and control signals are generated the cycle
before the data transfer takes place. All memory accesses are timed with the clock
CLK.
For each interface there are different types of memory access:
•
•
•
•
The ARM9E-S can operate in both big-endian and little-endian memory configurations
and this is selected by the CFGBIGEND input. The endian configuration affects both
interfaces, so you must take care when designing the memory interface logic to allow
correct operation of the processor core.
For system programming purposes, you must normally provide some mechanism for
the data interface to access instruction memory. There are two main reasons for this:
•
•
A typical implementation of an ARM9E-S based cached processor has Harvard caches
and a unified memory structure beyond the caches, therefore giving the data interface
access to the instruction memory space. However, for an SRAM-based system, you
cannot use this technique, and you must use an alternative method.
It is not necessary for the instruction interface to have access to the data memory area
unless the processor needs to execute code from data memory.
Nonsequential
Sequential
Internal
Coprocessor transfer (for the data interface).
The use of in-line data for literal pools is very common. This data is fetched using
the data interface but is normally contained in the instruction memory space.
To enable debug using the JTAG interface it must be possible to download code
into the instruction memory. This code has to be written to memory through the
data interface, because the instruction interface is read-only. In this case it is
essential for the data interface to have access to the instruction memory.
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ARM DDI 0165B