SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 107

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.12
ARM DDI 0165B
CLK
CLKEN
DnMREQ,
DSEQ,
DMORE
RDATA[31:0]
(Read)
Address class
signals
Use of CLKEN to control bus cycles
The pipelined nature of the ARM9E-S bus interface means that there is a distinction
between clock cycles and bus cycles. You can use CLKEN to stretch a bus cycle, so that
it lasts for many clock cycles. The CLKEN input extends the timing of bus cycles in
increments of complete CLK cycles:
•
•
The CLKEN input extends bus cycles on both the instruction and data interfaces when
asserted.
In the pipeline, the address class signals and the memory request signals are ahead of
the data transfer by one bus cycle. In a system using CLKEN this can be more than one
CLK cycle. This is illustrated in Figure 4-12, which shows CLKEN being used to
extend a nonsequential cycle. In the example, the first N cycle is followed by another
N cycle to an unrelated address, and the address for the second access is broadcast
before the first access completes.
When designing a memory controller, you must sample the values of InMREQ, ISEQ,
DnMREQ, DSEQ, DMORE, and the address class signals only when CLKEN is
HIGH. This ensures that the state of the memory controller is not accidentally updated
Address 1
N cycle
when CLKEN is HIGH on the rising edge of CLK, a bus cycle completes
when CLKEN is sampled LOW, the bus cycle is extended.
Note
Copyright © 2000 ARM Limited. All rights reserved.
First bus cycle
Address 2
N cycle
data 1
Read
Second bus cycle
Figure 4-12 Use of CLKEN
Next cycle type
Next address
Memory Interface
data 2
Read
4-31