SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 279

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.11
ARM DDI 0165B
Vector catching
The ARM9E-S EmbeddedICE-RT logic contains hardware that allows efficient
trapping of fetches from the vectors during exceptions. This is controlled by the vector
catch register. If one of the bits in this register is set HIGH and the corresponding
exception occurs, the processor enters debug state as if a breakpoint has been set on an
instruction fetch from the relevant exception vector.
For example, if the processor executes a SWI instruction while bit 2 of the vector catch
register is set, the ARM9E-S fetches an instruction from location
hardware detects this access and forces the internal IBREAKPT signal HIGH into the
ARM9E-S control logic. This, in turn, forces the ARM9E-S to enter debug state.
The behavior of the hardware is independent of the watchpoint comparators, leaving
them free for general use. The vector catch register is sensitive only to fetches from the
vectors during exception entry. Therefore, if code branches to an address within the
vectors during normal operation, and the corresponding bit in the vector catch register
is set, the processor is not forced to enter debug state.
In monitor mode debug, vector catching is disabled on Data Aborts and Prefetch Aborts
to avoid the processor being forced into an unrecoverable state as a result of the aborts
that are generated for the monitor mode debug.
Copyright © 2000 ARM Limited. All rights reserved.
0x8
. The vector catch
Debug in depth
C-39