SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 152

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface and EmbeddedICE-RT
7.6
7.6.1
7-14
ARM9E-S core clock domains
Clocks and synchronization
Multi-ICE
interface
pads
The ARM9E-S has a single clock, CLK, that is qualified by two clock enables:
•
•
During normal operation, CLKEN conditions CLK to clock the core. When the
ARM9E-S is in debug state, DBGTCKEN conditions CLK to clock the core.
If the system and test clocks are asynchronous, they must be synchronized externally to
the ARM9E-S macrocell. The ARM Multi-ICE debug agent directly supports one or
more cores within an ASIC design. To synchronize off-chip debug clocking with the
ARM9E-S macrocell requires a three-stage synchronizer. The off-chip device (for
example, Multi-ICE) issues a TCK signal, and waits for the RTCK (Returned TCK)
signal to come back. Synchronization is maintained because the off-chip device does
not progress to the next TCK until after RTCK is received. Figure 7-7 shows this
synchronization.
TDO
RTCK
TCK
TMS
TDI
CLKEN controls access to the memory system
DBGTCKEN controls debug operations.
CLK
Copyright © 2000 ARM Limited. All rights reserved.
D
Q
TCK synchronizer
D
Q
D
Q
Figure 7-7 Clock synchronization
CLK
Input sample and hold
D
EN
Q
CLK
D
EN
Q
ARM DDI 0165B
DBGTCKEN
DBGTDO
DBGTMS
DBGTDI
CLK