SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 118

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM9E-S Coprocessor Interface
6.1
6.1.1
6.1.2
6-2
About the coprocessor interface
Coprocessor pipeline operates in step with the ARM9E-S
Coprocessor pipeline one cycle behind the ARM9E-S
The ARM9E-S supports the connection of coprocessors. All types of ARM
coprocessors are supported. Coprocessors determine the instructions they need to
execute using a pipeline follower in the coprocessor. As each instruction arrives from
memory, it enters both the ARM pipeline and the coprocessor pipeline. The coprocessor
determines when an instruction is being fetched by the ARM9E-S, so that the
instruction can be loaded into the coprocessor, and the pipeline follower advanced.
The coprocessor can be run either in step with the ARM9E-S pipeline, or one cycle
behind, depending on the timing priorities. The implications of the two approaches are
discussed in:
•
•
In this case, the pipeline follower inside the coprocessor matches that of the ARM9E-S
exactly. This complicates the timing of key signals such as the INSTR and CLKEN
inputs, because these now become more heavily loaded and therefore incur more delay.
For this reason, this method is only recommended for tightly integrated coprocessors
such as CP15, the system coprocessor.
This method is recommended for external coprocessors. A coprocessor interface block
pipelines the instruction and control signals so that the loading is reduced on these
critical signals. This means that the pipeline in the coprocessor operates one cycle
behind the ARM9E-S pipeline. The disadvantage of this is that outputs of the
coprocessor are still expected in the correct pipeline stage, as seen from the ARM9E-S.
The most critical signal in this situation is likely to be CHSD[1:0], the coprocessor
decode handshake signal. This must return the availability of the coprocessor by the end
of the decode cycle, as seen by the ARM9E-S. This is equivalent to the fetch cycle of
the coprocessor pipeline, and therefore there is not much time to generate this signal.
This means that the design might have to insert wait states for external coprocessor
accesses.
There are three classes of coprocessor instructions:
•
•
•
Coprocessor pipeline operates in step with the ARM9E-S
Coprocessor pipeline one cycle behind the ARM9E-S.
LDC
MCR
CDP
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STC
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