SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 155

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.8.2
ARM DDI 0165B
Debug comms channel control register
The debug comms channel control register is read-only.
synchronized handshaking between the processor and the debugger. The debug comms
channel control register is shown in Figure 7-8.
The function of each register bit is described below:
Bits 31:28
Bits 27:2
Bit 1
Bit 0
1. The control register should be viewed as read-only. However, the debugger can clear the
R bit by performing a write to the debug comms channel control register. This feature
must not be used under normal circumstances.
Copyright © 2000 ARM Limited. All rights reserved.
Contain a fixed pattern that denotes the EmbeddedICE version
number (in this case 0011).
Are reserved.
Denotes if the comms data write register is available (from the
viewpoint of the processor). Seen from the processor, if the
comms data write register is free (W=0), new data can be written.
If the register is not free (W=1), the processor must poll until
W=0.
Seen from the debugger, when W=1, some new data has been
written that can then be scanned out.
Denotes if there is new data in the comms data read register. Seen
from the processor, if R=1, there is some new data that can be read
using an
Seen from the debugger, if R=0, the comms data read register is
free, and new data may be placed there through the scan chain. If
R=1, this denotes that data previously placed there through the
scan chain has not been collected by the processor, and so the
debugger must wait.
MRC
Figure 7-8 Debug comms channel control register
instruction.
Debug Interface and EmbeddedICE-RT
1
The register controls
7-17