SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 229

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
Name
DBGCOMMRX
Communications
channel receive
DBGCOMMTX
Communications
channel transmit
DBGACK
Debug
acknowledge
DBGEN
Debug enable
DBGRQI
Internal debug
request
EDBGRQ
DBGEXT[1:0]
EmbeddedICE
external input
DBGINSTREXEC
DBGINSTRVALID
DBGRNG[1:0]
EmbeddedICE
Rangeout
TAPID[31:0]
Boundary scan
ID code
Copyright © 2000 ARM Limited. All rights reserved.
Direction
Output
Output
Output
Input
Output
Input
Input
Output
Output
Output
Input
When HIGH, this signal denotes that the comms
When HIGH, this signal denotes that the comms
When HIGH, indicates that the processor is in debug
Instruction valid. Indicates that the instruction in the
This output indicates that the corresponding
Description
channel receive buffer contains valid data waiting to
be read by the ARM9E-S.
channel transmit buffer is empty.
state.
This input signal allows the debug features of the
processor to be disabled. This signal must be LOW
when debugging is not required.
This signal represents the state of bit 1 of the debug
control register that is combined with EDBGRQ and
presented to the core debug logic.
External debug request. An external debugger may
force the processor to enter debug state by asserting
this signal.
This input to the EmbeddedICE logic allows
breakpoints and watchpoints to be dependent on
external conditions.
Instruction executed. Indicates that the instruction in
the Execute stage of the processors pipeline has been
executed.
Execute stage of the processors pipeline was valid
and has been executed (unless it failed its conditions
codes).
EmbeddedICE watchpoint unit has matched the
conditions currently present on the address, data and
control buses. This signal is independent of the state
of the enable control bit of the watchpoint unit.
This input specifies the ID code value shifted out on
DBGTDO when the IDCODE instruction is entered
into the TAP controller.
Table A-6 Debug signals (continued)
Signal Descriptions
A-9