SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 176

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.10
8.10.1
8-16
Multiply and multiply accumulate
Interlocks
The multiply instructions make use of special hardware that implements integer
multiplication. All cycles except the last are internal.
During the first (Execute) stage of a multiply instruction, the multiplier and
multiplicand operands are read onto the A and B buses, on which the multiplier unit is
connected. The first stage of the multiplier performs Booth recoding and partial product
summation, using 16 bits of the multiplier operand each cycle.
During the second (Memory) stage of a multiply instruction, the partial product result
from the Execute stage is added with an optional accumulate term (read onto the C bus)
and a possible feedback term from a previous multiply step for multiplications which
require additional cycles.
In Thumb state, only the
The multiply unit in ARM9E-S operates in both the Execute and Memory stage of the
pipeline. Because of this, the multiplier result is not available until the end of the
Memory stage of the pipeline. If the following instruction requires the use of the
multiplier result, then it must be interlocked so that the correct value is available. This
applies to all instructions that require the multiply result for the first Execute cycle or
first Memory cycle of the instruction except for multiply accumulate instructions using
the previous multiply result as the accumulator operand.
As an example, the following sequence incurs a single-cycle interlock:
MUL
SUB
The following cycle also incurs a single-cycle interlock:
MLA
STR
The following example does not incur an interlock:
MLA
MLA
Note
Copyright © 2000 ARM Limited. All rights reserved.
r0, r1, r2
r4, r0, r3
r0, r1, r2, r3
r0, [r8]
r0, r1, r2, r0
r0, r3, r4, r0
MULS
and
MLAS
operations are possible.
ARM DDI 0165B