SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 74

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Device Reset
3.2.2
3.2.3
3.2.4
3-4
CPU reset
EmbeddedICE-RT reset
Normal operation
A CPU or warm reset initializes the majority of the ARM9E-S CPU, excluding the
ARM9E-S TAP controller and the EmbeddedICE-RT unit. CPU reset is typically used
for resetting a system that has been operating for some time, for example, watchdog
reset.
Sometimes you might not want to reset the EmbeddedICE-RT unit when resetting the
rest of the ARM9E-S, for example, if EmbeddedICE-RT has been configured to
breakpoint (or capture) fetches from the reset vector.
For CPU reset, both the leading and trailing edges of nRESET must be set up and held
about the rising edge of CLK. This ensures that there are no metastability issues
between the ARM9E-S and the EmbeddedICE-RT unit.
EmbeddedICE-RT reset initializes the state of the ARM9E-S TAP controller and the
EmbeddedICE-RT unit. EmbeddedICE-RT reset is typically used by the Multi-ICE
module for hot connection of a debugger to a system.
EmbeddedICE-RT reset allows initialization of the EmbeddedICE-RT unit without
affecting the normal operation of the ARM9E-S.
For EmbeddedICE-RT reset, both the leading and trailing edges of DBGnTRST must
be set up and held about the rising edge of CLK. This ensures that there are no
metastability issues between the ARM9E-S and the EmbeddedICE-RT unit.
Refer to Clocks and synchronization on page 7-14 for more details of synchronization
between the Multi-ICE and ARM9E-S.
During normal operation, neither CPU reset nor EmbeddedICE-RT reset is asserted.
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ARM DDI 0165B