SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 85

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

4.6.1
ARM DDI 0165B
Instruction interface, nonsequential cycles
The ARM9E-S instruction interface has three types of memory cycle:
Nonsequential cycle
Sequential cycle
Internal cycle
A nonsequential instruction fetch is the simplest form of an ARM9E-S instruction
interface cycle, and occurs when the ARM9E-S requests a transfer to or from an address
that is unrelated to the address used in the preceding cycle. The memory controller must
initiate a memory access to satisfy this request.
The address class signals and the InMREQ, ISEQ = N cycle signals are broadcast on
the instruction interface bus. At the end of the next bus cycle the instruction is
transferred to the CPU from memory. This is shown in Figure 4-2.
Copyright © 2000 ARM Limited. All rights reserved.
CLK
InMREQ,
ISEQ
Address class
signals
INSTR[31:0]
During this the ARM9E-S core requests a transfer to or from an
address that is unrelated to the address used in the preceding cycle.
During this the ARM9E-S core requests a transfer to or from an
address that is either one word, or one halfword greater than the
address used in the preceding cycle.
During this the ARM9E-S core does not require a transfer because
it is performing an internal function, and no useful prefetching can
be performed at the same time.
Figure 4-2 Nonsequential instruction fetch cycle
Address
N cycle
N cycle
Instruction
data
Memory Interface
4-9