SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 259

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0165B
The use of r0 as the base register for the
register.
After you have determined the values in the bank of registers available in the current
mode, you might want to access the other banked registers. To do this, you must change
mode. Normally, a mode change can occur only if the core is already in a privileged
mode. However, while in debug state, a mode change can occur from any mode into any
other mode.
The debugger must restore the original mode before exiting debug state. For example,
if the debugger has been requested to return the state of the User mode registers and FIQ
mode registers, and debug state is entered in Supervisor mode, the instruction sequence
can be as shown in Example C-1.
Example C-1 Determining the core state
STMIA R0, {R0-R15}; Save current registers
MRS
STR
BIC
ORR
MSR
STMIA R0, {R13,R14}; Save registers not previously visible
ORR
MSR
STMIA R0, {R8-R14}; Save banked FIQ registers
All these instructions execute at debug speed. Debug speed is much slower than system
speed. This is because between each core clock, 67 clocks occur in order to shift in an
instruction, or shift out data. Executing instructions this slowly is acceptable for
accessing the core state because the ARM9E-S is fully static. However, you cannot use
this method for determining the state of the rest of the system.
While in debug state, you can only scan the following ARM or Thumb instructions into
the instruction pipeline for execution:
•
•
•
•
all data processing operations
all load, store, load multiple, and store multiple instructions
MSR
B
R0, CPSR
R0, [R0]; Save CPSR to determine current mode
R0, 0x1F; Clear mode bits
R0, 0x10; Select User mode
CPSR, R0; Enter User mode
R0, 0x01; Select FIQ mode
CPSR, R0; Enter FIQ mode
,
Note
Copyright © 2000 ARM Limited. All rights reserved.
BL
and
, and
MRS
BX
.
STM
is only for illustration, and you can use any
Debug in depth
C-19