SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 180

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Times
8.11
8.11.1
8-20
QADD, QDADD, QSUB, and QDSUB
Interlocks
This class of instructions normally takes one cycle to execute and is only available in
ARM state.
The instructions in this class use both the Execute and Memory stages of the pipeline.
Because of this, the result of an instruction in this class is not available until the end of
the Memory stage of the pipeline. If a following instruction requires the use of the
result, then it must be interlocked so that the correct value is available. This applies to
all instructions that require the result for the first Execute cycle. Instructions that require
the result of a
interlock.
As an example, the following sequence incurs a single-cycle interlock:
QADD
SUB
The following cycle does not incur a single-cycle interlock:
QDSUB
STR
The following example does not incur an interlock:
QADD
MLA
Table 8-17 shows the cycle timing for
and without interlocks.
Cycle
Normal
Interlock
Copyright © 2000 ARM Limited. All rights reserved.
r0, r1, r2
r4, r0, r3
r0, r1, r2
r0, [r8]
r0, r4, r5
r0, r3, r4, r0
1
1
2
QADD
IA
pc+3i
pc+3i
pc+3i
or similar instruction for the first Memory cycle do not incur an
Table 8-17 QADD, QDADD, QSUB, and QDSUB cycle timing
InMREQ,
ISEQ
S cycle
I cycle
S cycle
QADD
INSTR
(pc+2i)
(pc+3i)
(pc+2i)
-
(pc+3i)
,
QDADD
,
QSUB
DA
-
-
-
, and
DnMREQ,
DSEQ
I cycle
b
I cycle
I cycle
QDSUB
instructions with
ARM DDI 0165B
RDATA/
WDATA
-
-