SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 65

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.9.7
ARM DDI 0165B
Aborts
Irrespective of whether exception entry is from ARM state or Thumb state, an IRQ
handler returns from the interrupt by executing:
SUBS PC,R14_irq,#4
You can disable IRQ exceptions within a privileged mode by setting the CPSR I flag.
When the I flag is clear, the ARM9E-S checks for a LOW level on the output of the
nIRQ register at the end of each instruction.
FIQs and IRQs are disabled when an IRQ occurs. Nested interrupts are allowed but it is
up to you to save any corruptible registers and to re-enable FIQs and interrupts.
An abort indicates that the current memory access cannot be completed. An abort is
signaled by one of the two external abort input pins, IABORT and DABORT.
There are two types of abort:
•
•
IRQs are disabled when an abort occurs.
Prefetch Abort
This is signaled by an assertion on the IABORT input pin and checked at the end of
each instruction fetch.
When a Prefetch Abort occurs, the ARM9E-S marks the prefetched instruction as
invalid, but does not take the exception until the instruction reaches the Execute stage
of the pipeline. If the instruction is not executed, for example because a branch occurs
while it is in the pipeline, the abort does not take place.
After dealing with the cause of the abort, the handler executes the following instruction
irrespective of the processor operating state:
SUBS PC,R14_abt,#4
This action restores both the PC and the CPSR, and retries the aborted instruction.
Data Abort
This is signaled by an assertion on the DABORT input pin and checked at the end of
each data access, both read and write.
Prefetch Abort
Data Abort on page 2-23.
Copyright © 2000 ARM Limited. All rights reserved.
Programmer’s Model
2-23