SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 242

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug in depth
C.1
C.1.1
C-2
Scan chains and JTAG interface
Debug scan chains
There are two JTAG-style scan chains within the ARM9E-S. These allow debugging
and EmbeddedICE-RT programming.
The scan chains allow commands to be serially shifted into the ARM core, allowing the
state of the core and the system to be interrogated. The JTAG interface requires only
five pins on the package.
A JTAG style Test Access Port (TAP) controller controls the scan chains. For further
details of the JTAG specification, refer to IEEE Standard 1149.1 - 1990 Standard Test
Access Port and Boundary-Scan Architecture.
The two scan paths used for debug purposes are referred to as scan chain 1 and scan
chain 2, and are shown in Figure C-1.
Scan chain 2
Copyright © 2000 ARM Limited. All rights reserved.
EmbeddedICE-RT
ARM9E-S
Figure C-1 ARM9E-S scan chain arrangements
TAP controller
ARM9E-S
Scan chain 1
ARM9E-S
ARM DDI 0165B
core