SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 193

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.18
8.18.1
ARM DDI 0165B
Cycle
Normal
1 cycle interlock
Data swap
Interlocks
1
2
1
2
3
A data swap is similar to a back-to-back load and store instruction. The data is read from
external memory in the second cycle and the contents of the register are written to the
external memory in the third cycle (which is merged with the first Execute cycle of the
next instruction).
The data swapped can be a byte or word quantity.
The swap operation might be aborted in either the read or the write cycle. An aborted
swap operation does not affect the destination register.
Data swap instructions are not available in Thumb state.
The DLOCK output of ARM9E-S is driven HIGH for both read and write cycles to
indicate to the memory system that it is an atomic operation.
A swap operation can cause one and two-cycle interlocks in a similar fashion to a load
register instruction.
Table 8-25 shows the cycle timing for the basic data swap operation.
IA
pc+3i
pc+3i
pc+3i
pc+3i
pc+3i
Note
Copyright © 2000 ARM Limited. All rights reserved.
I cycle
InMREQ,
ISEQ
S cycle
I cycle
I cycle
S cycle
INSTR
(pc+2i)
-
(pc+3i)
(pc+2i)
-
-
(pc+3i)
DA
da
da
da
da
-
DnMREQ,
DSEQ
N cycle
N cycle
N cycle
N cycle
I cycle
Table 8-25 Data swap cycle timing
RDATA
(da)
-
(da)
-
-
Instruction Cycle Times
WDATA
-
Rd
-
Rd
-
8-33