SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 157

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.8.4
ARM DDI 0165B
Communications using the comms channel
A typical use of this bit is by a monitor mode debug aware abort handler. This examines
the DbgAbt bit to determine whether the abort was externally or internally generated. If
the DbgAbt bit is set, the abort handler initiates communication with the debugger over
the comms channel.
You can send and receive messages using the comms channel. These are described in:
•
•
Sending a message to the debugger
Before the processor can send a message to the debugger, it must check that the comms
data write register is free for use by finding out if the W bit of the debug comms control
register is clear.
The processor reads the debug comms control register to check the status of the W bit:
•
•
When the W bit is clear, a message is written by a register transfer to coprocessor 14.
As the data transfer occurs from the processor to the comms data write register, the W
bit is set in the debug comms control register.
The debugger has two options available for reading data from the comms data write
register:
•
•
Sending a message to the debugger
Receiving a message from the debugger on page 7-20.
If the W bit is clear, the comms data write register is clear.
If the W bit is set, previously written data has not been read by the debugger. The
processor must continue to poll the control register until the W bit is clear.
Poll the debug comms channel control register before reading the comms data
written. If the W bit is set, there is valid data present in the debug comms data
write register. The debugger can then read this data and scan the data out. The
action of reading the data clears the debug comms channel control register W bit.
Then the communications process can begin again.
Poll the comms data write register, obtaining data and valid status. The data
scanned out consists of the contents of the comms data write register (which
might or might not be valid), and a flag that indicates whether the data read is
valid or not. The status flag is present in the Addr[0] bit position of scan chain 2
when the data is scanned out. See Test data registers on page C-10 for details of
scan chain 2.
Copyright © 2000 ARM Limited. All rights reserved.
Debug Interface and EmbeddedICE-RT
7-19