SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 108

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

CLK
CLKEN
DnMREQ,
DSEQ,
DMORE,
DnSPEC
Address class
signals
Memory Interface
4.12.1
4-32
Withdrawal of memory requests in waited cycles
during a waited cycle. In addition, the ARM9E-S can alter the request for a subsequent
memory cycle during a waited (CLKEN LOW) cycle. See Withdrawal of memory
requests in waited cycles.
The ARM9E-S can alter the value of the memory request and address signals during
cycles in which CLKEN is LOW. This is done to improve the worst case interrupt
latency of ARM9E-S systems. For example, a pending memory request can be
withdrawn if the core is about to take an interrupt and the access is unnecessary.
The ARM9E-S does not alter or withdraw any access to which it is committed. An
access is said to be committed when the address and request signals are sampled on the
rising edge of CLK when CLKEN is HIGH.
The ARM9E-S only attempts to alter or withdraw an uncommitted access during the
extended (or waited) bus cycle of a previous access. Alteration of the next memory
request during a waited bus cycle is shown in Figure 4-13.
This behavior affects the IA, InMREQ, ISEQ, DA, DnMREQ, DSEQ, DMORE, and
DnSPEC outputs of the ARM9E-S.
Request 1
Address 1
N cycle
Note
Copyright © 2000 ARM Limited. All rights reserved.
Figure 4-13 Alteration of next memory request during waited bus cycle
Ignored
Ignored
First bus cycle
Ignored
Ignored
Internal cycle
Second bus cycle
ARM DDI 0165B