SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 271

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.10.4 Watchpoint control registers
ARM DDI 0165B
The format of the control registers depends on how bit 3 is programmed.
If bit 3 of the control register is programmed to a 1, the breakpoint comparators examine
the data address, data, and control signals.
In this case, the format of the control register is as shown in Figure C-8.
You cannot mask bit 8 and bit 3.
Data comparison bit functions are described in Table C-5.
Bit
number
0
2:1
4
5
Note
Copyright © 2000 ARM Limited. All rights reserved.
Name
DnRW
DMAS[1:0]
DnTRANS
DBGEXT
Table C-5 Watchpoint control register for data comparison functions
Figure C-8 Watchpoint control register for data comparison
Function
Compares against the data not read/write signal from the core in
order to detect the direction of the data data bus activity. DnRW
is 0 for a read, and 1 for a write.
Compares against the DMAS[1:0] signal from the core in order
to detect the size of the data data bus activity.
Compares against the data not translate signal from the core in
order to determine between a User mode (DnTRANS = 0) data
transfer, and a privileged mode (DnTRANS = 1) transfer.
Is an external input into the EmbeddedICE-RT logic that allows
the watchpoint to be dependent upon some external condition.
The DBGEXT input for watchpoint 0 is labeled DBGEXT[0],
and the DBGEXT input for watchpoint 1 is labeled
DBGEXT[1].
Debug in depth
C-31