SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 112

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Interrupts
5-4
takes the FIQ exception in a later cycle, even if the nFIQ input is subsequently
deasserted.
There are several approaches that you can adopt to ensure that interrupts are not enabled
too early on the ARM9E-S. The best approach is highly dependent on the overall
system, and can be a combination of hardware and software.
nFIQ or nIRQ) typically does not take effect until after the Memory stage of that
instruction. The instruction that re-enables interrupts on the ARM9E-S can cause the
ARM9E-S to be sensitive to interrupts as early as the Execute stage of that instruction.
For example, consider the following instruction sequence:
STR r0, [r1] ;Write to interrupt controller, clearing interrupt
SUBS pc, r14, #4 ;Return from interrupt routine
The execution of this code sequence is illustrated in Figure 5-1.
In Figure 5-1, the
nFIQ input until cycle 4. The
interrupts during cycle 3.
Because of this timing relationship, the ARM9E-S retakes the FIQ exception in this
example.
The FIQDIS (and similarly IRQDIS) output from the ARM9E-S indicates when the
ARM9E-S is sensitive to the state of the nFIQ (nIRQ) input (0 for sensitive, 1 for
insensitive). If nFIQ is asserted in the same cycle that FIQDIS is LOW, the ARM9E-S
STR r0, [r1]
SUBS pc, r14, #4
Copyright © 2000 ARM Limited. All rights reserved.
STR
to the interrupt controller does not cause the deassertion of the
SUBS
instruction causes the ARM9E-S to be sensitive to
Figure 5-1 Retaking the FIQ exception
ARM DDI 0165B