SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 267

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

C.9
C.9.1
C.9.2
C.9.3
ARM DDI 0165B
Priorities and exceptions
Breakpoint with Prefetch Abort
Interrupts
Data Aborts
When a breakpoint or a debug request occurs, the normal flow of the program is
interrupted. Therefore you can treat debug as another type of exception. The interaction
of the debugger with other exceptions is described in Behavior of the program counter
during debug on page C-24. This section covers the priorities.
When a breakpointed instruction fetch causes a Prefetch Abort, the abort is taken and
the breakpoint is disregarded. Normally, Prefetch Aborts occur when, for example, an
access is made to a virtual address that does not physically exist, and the returned data
is therefore invalid. In such a case, the normal action of the operating system is to swap
in the page of memory, and to return to the previously invalid address. This time, when
the instruction is fetched, and providing the breakpoint is activated (it might be
data-dependent), the ARM9E-S enters debug state.
The Prefetch Abort, therefore, takes higher priority than the breakpoint.
When the ARM9E-S enters debug state, interrupts are automatically disabled.
If an interrupt is pending during the instruction prior to entering debug state, the
ARM9E-S enters debug state in the mode of the interrupt. On entry to debug state, the
debugger cannot assume that the ARM9E-S is in the mode expected by your program.
The ARM9E-S must check the PC, the CPSR, and the SPSR to determine accurately the
reason for the exception.
Debug, therefore, takes higher priority than the interrupt, but the ARM9E-S does
recognize that an interrupt has occurred.
When a Data Abort occurs on a watchpointed access, the ARM9E-S enters debug state
in Abort mode. The watchpoint, therefore, has higher priority than the abort, but the
ARM9E-S remembers that the abort happened.
Copyright © 2000 ARM Limited. All rights reserved.
Debug in depth
C-27