SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 124

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM9E-S Coprocessor Interface
6.3
6-8
MCR/MRC
ARM processor pipeline
WDATA[31:0]
RDATA[31:0]
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InMREQ
MCR
Figure 6-3.
First InMREQ is driven LOW to denote that the instruction on INSTR[31:0] is
entering the decode stage of the pipeline. This causes the coprocessor to decode the new
instruction and drive CHSD[1:0] as required.
In the next cycle InMREQ is driven LOW to denote that the instruction has now been
issued to the Execute stage. If the condition codes pass, and the instruction is to be
executed, the PASS signal is driven HIGH and the CHSD[1:0] handshake bus is
examined by the core (it is ignored in all other cases).
(MCR)
(MRC)
PASS
CLK
and
Copyright © 2000 ARM Limited. All rights reserved.
MRC
cycles look very similar to
Figure 6-3 ARM9E-S MCR or MRC transfer timing
STC
or
LDC
. An example is shown in
ARM DDI 0165B