SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 187

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.14
8.14.1
ARM DDI 0165B
Load multiple registers
Interlocks
A load multiple (
registers transferred and whether the PC is in the list of registers transferred.
1.
2.
When a Data Abort occurs, the instruction continues to completion. The ARM9E-S
prevents all register writing after the abort. The ARM9E-S restores the modified base
pointer (which the load activity before the abort occurred might have overwritten).
When the PC is in the list of registers to be loaded, the ARM9E-S invalidates the current
contents of the instruction pipeline. The PC is always the last register to be loaded, so
an abort at any point prevents the PC from being overwritten.
LDM
POP{Rlist, PC}
An
last data value transferred. This is similar to the interlock cases present with a single
word register load. There is an exception to this case for a single-word
to the presence of an idle cycle at the end of a single-word
exists.
For example, the following sequence incurs a single-cycle interlock:
LDMIA r0, {r1-r2}
ADD
The following sequence incurs a single-cycle interlock:
LDMIA r0, {r1-r2}
STR
The following sequence does not incur an interlock:
LDMIA r0, {r1}
STR
LDM
with
During the first cycle, the ARM9E-S calculates the address of the first word to be
During the second and subsequent cycles, ARM9E-S reads the data requested in
transferred, while performing an instruction prefetch.
the previous cycle and calculates the address of the next word to be transferred.
The new value for the base register is calculated.
r3, r2, r4
r2, [r3]
r1, [r2]
Note
Copyright © 2000 ARM Limited. All rights reserved.
instruction can cause an interlock if a following instruction is dependent on the
destination = PC
LDM
equates to an
) takes several cycles to execute, depending on the number of
cannot be executed in Thumb state. However,
LDM
with
destination = PC
LDM
, no interlock condition
.
Instruction Cycle Times
LDM
where, due
8-27