SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 132

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM9E-S Coprocessor Interface
6.8
6-16
CDP: ARM processor pipeline
Privileged instructions
LATECANCEL
INSTR[31:0]
CHSD[1:0]
CHSE[1:0]
InTRANS
/InM[4:0]
InMREQ
PASS
CLK
Mode change
The coprocessor might restrict certain instructions for use in privileged modes only. To
do this, the coprocessor has to track the InTRANS output. Figure 6-8 shows how
InTRANS changes after a mode change.
The first two CHSD responses are ignored by the ARM9E-S because it is only the final
CHSD response, as the instruction moves from Decode into Execute, that counts. This
allows the coprocessor to change its response as InTRANS/InM changes.
Copyright © 2000 ARM Limited. All rights reserved.
Figure 6-8 ARM9E-S privileged instructions
ARM DDI 0165B