DF2166VT33WV Renesas Electronics America, DF2166VT33WV Datasheet - Page 132

• Manufacturer Part Number: DF2166VT33WV
• Description: MCU 16BIT FLASH 3V 512K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2166VT33WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 5.6
Interrupt
Control Mode
0
1
[Legend]
O:
IM:
PR:
—:
5.6.1
In interrupt control mode 0, interrupts other than NMI are masked by ICR and the I bit of the CCR
in the CPU. Figure 5.5 shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. According to the interrupt control level specified in ICR, the interrupt controller accepts an
3. If the I bit in CCR is set to 1, only NMI and address break interrupt requests are accepted by
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 3.00, 03/04, page 90 of 830
interrupt request is sent to the interrupt controller.
interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request
with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt
request with the highest priority is accepted according to the priority order, an interrupt
handling is requested to the CPU, and other interrupt requests are held pending.
the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted. KIN, WUE, and EVENTI interrupts are enabled or disabled
by the I bit.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
interrupts.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt operation control performed
Used as an interrupt mask bit
Sets priority
Not used
Interrupt Control Mode 0
Operations and Control Signal Functions in Each Interrupt Control Mode
INTM1
0
Setting
INTM0
0
1
O
O
I
IM
IM
Interrupt Acceptance Control
3-Level Control
UI
—
IM
ICR
PR
PR
Default Priority
Determination
O
O
T (Trace)
—
—